This invention relates to digital data processing systems which are comprised of a plurality of devices that send messages to each other over a time-shared bus. Each device in the system may be any type of digital equipment. For example, one device might be a digital processor, another device might be a disc, another device might be a printer, etc.
One such prior art digital processing system, which is utilized by NCR, is illustrated in FIG. 1A. There, the plurality of devices are indicated by reference numerals 10-1 through 10-N; and the time-shared bus over which they send messages is indicated by reference numeral 11. All message transfers on bus 11 are synchronized by a fixed frequency clock signal which is generated by a bus controller 12 on a line 13.
Controller 12 also determines the priority by which the devices send messages over bus 11. To that end, controller 12 receives a "request" signal from each device over separate control lines 14-1 through 14-N; and it sends a "request granted" signal back to each device over separate control lines 15-1 through 15-N. These control lines are not time-shared by the devices.
Also, controller 12 monitors all messages on bus 11 to determine if a parity error occurs. If an error does occur, then controller 12 sends a signal on another separate control line 16 to the device which received the erroneous message.
An undesirable aspect of the FIG. 1A system is that if a device receives a message which requires a response message to be sent, that response message cannot be sent immediately. Instead, the receiving device must first "ask" bus controller 12 if it can use the bus. Typically, several other devices will transmit messages on the bus before the receiving device is permitted to send its response. Thus communication between devices on bus 11 occurs in a random illogical order.
Another undesirable aspect of the FIG. 1A system is that too many separate control lines are required for operating bus 11. These are lines 14-1 through 14-N, 15-1 through 15-N, and 16 as described above. This drawback is most severe for large systems, because the number of control lines increases as the number of devices increases.
Further, the FIG. 1A system is totally dependent on bus controller 12 for its operation. That is, the system simply will not work when controller 12 needs repair. This is true even though devices 14-1 through 14-N may be completely operational.
Another prior art data processing system which includes a time-shared bus is illustrated in FIG. 1B. That system is utilized by IBM. There, the devices are indicated by reference numerals 20-1 through 20-N; and the time-shared bus on which messages are sent is indicated by reference numeral 21. All message transfers occur between one of the devices and bus controller 22, which is also called a channel.
In operation, bus controller 22 sends spaced apart polling pulses down a separate control line 23. A path for these pulses to pass serially through each device is established by the placement of three jumper wires as indicated by dashed lines in FIG. 1B. Any device may transmit a message to controller 22 only after it receives a polling pulse on line 23, blocks that pulse from traveling further down the line, and sends a signal on another control line 24 which tells controller 22 to stop generating pulses until the message is sent. Each device generates its own asynchronous clocking signals on respective lines 25-1 through 25-4 to transfer messages on bus 21. A device which has no message to send simply allows the pulses on line 23 to pass to the next device.
Once a device obtains the use of the bus 21, messages can be sent from that device to bus controller 22 and the controller can respond by immediately sending another message back to that same device. But the channel cannot respond by sending a message back to a second device. Also, one device cannot send a message directly to another device.
The IBM system does utilize fewer control lines than does the system of FIG. 1A. But even so, the IBM system still requires some separate control lines and still depends on a separate bus controller for its operation. Further, the above reduction in control lines 1B are obtained only at the cost of making the priority by which a device may obtain the bus very inflexible. That priority is limited by the device's position on the bus. Device 20-4 can have either the first or last priority; device 20-3 can have either first or second or next-to-last or last priority; etc.
Accordingly, it is a primary objective of the invention to provide an improved data processing system.
Another object of the invention is to provide a data processing system in which a plurality of devices can carry on conversations with each other in any logical sequence without interruption.
Another object of the invention is to provide a data processing system having a time-shared bus over which a plurality of digital devices communicate without any separate bus controller or separate control lines.
Another object of the invention is to provide an improved digital device for transmitting messages on a time-shared bus.
Still another object of the invention is to provide an improved digital device for selectively receiving messages on a time-shared bus.